1. Field of Invention
The invention relates to a semiconductor device. More particularly, the invention relates to an insulated gate semiconductor device with low on-resistance, used for a high breakdown voltage IC to control a large current, such as an IC for a switching power source. The invention also relates to an IC for driving an automotive power system and to an IC for a plasma display panel driver.
2. Prior Art
In recent years, with the rapid spread of portable information appliances and the development of information technology, power ICs containing power MOSFETs are becoming more important. As for a power IC with a lateral power MOSFET and a control circuit thereof being integrated together, expectations are placed on downsizing, lowered power consumption, increased reliability and reduced cost. This is in contrast to a previous arrangement of a combination of a discrete power MOSFET with control and driving circuits. Thus, on the basis of CMOS processes, efforts are being actively carried out to develop high performance lateral power MOSFETs.
Recently, development activity has occurred regarding a trench lateral power MOSFET (hereinafter referred to as “TLPM”), because of its possibilities of further lowering on-resistance and of further increasing a packing density when being integrated into a power IC. Such improvements would be in comparison to on-resistance and packing densities in previous planar type lateral power MOSFETs. The TLPM may be classified into a type that provides a drain contact at a bottom of a trench (hereinafter referred to as “TLPM/D”) and a type that provides a source contact at the bottom of the trench (hereinafter referred to as “TLPM/S”) (see the Japanese patent publication JP-A-2002-353447, A. Sugi et al., “A 30V Class Extremely Low On-resistance Meshed Trench Lateral Power MOSFET,” IEEE IEDM, (US), 2002, Technical Digest, pp. 297–300, and N. Fujishima and 5 others, “A Low On-resistance Trench Lateral Power MOSFET in a 0.6 μm Smart Power Technology for 20–30V Applications,” IEEE IEDM, (US), 2002, Technical Digest, pp. 455–458).
Explanations will be made of a previous TLPM/D and a previous TLPM/S. FIG. 36 is a cross-sectional view showing an arrangement of the previous TLPM/D. As shown in FIG. 36, in a p−-semiconductor substrate 1, a trench 2 is formed. The trench 2 is filled with a gate insulator film 3, a gate electrode 4, an interlayer insulator film 5 and a buried electrode 6, which are provided from the sidewall of the trench 2 toward the center thereof in the order stated. In the lower half section of the trench 2, an insulator film 7 that is thicker than the gate insulator film 3 is provided for ensuring a withstand voltage.
The lower half section of the trench 2 is surrounded by an n−-extended drain region 8. Under the bottom of the trench 2 in the n−-extended drain region 8, an n+-drain region 9 is provided. The buried electrode 6 is electrically connected to the n+-drain region 9 at the bottom of the trench 2. Outside of the upper half section of the trench 2 is a p-base region 10.
Close outside the trench 2, in the upper section of the p-base region 10, an n+-source region 11 is provided. In the upper section of the p-base region 10, a p+-plug region 12 is provided. To the top end of the buried electrode 6, a drain electrode 13 is electrically connected. A source electrode 14 penetrates through an interlayer insulator film 15 so as to electrically connect to both the n+-source region 11 and the p+-plug region 12 on the surface of the substrate 1.
FIG. 37 is a cross-sectional view showing an arrangement of the previous TLPM/S. As shown in FIG. 37, a trench 2, formed in a p−semiconductor substrate 1, is filled with a gate insulator film 3, a gate electrode 4, an interlayer insulator film 5 and a buried electrode 6, which are provided from the sidewall of the trench 2 toward the center thereof in the order stated. Close outside the upper half section of the trench 2, an insulator film 7 that is thicker than the gate insulator film 3 is provided for ensuring a withstand voltage.
The lower half section of the trench 2 is surrounded by a p-base region 10. Under the bottom of the trench 2 in the p-base region 10, an n+-source region 11 is provided. The buried electrode 6 is electrically connected to the n+-source region 11 at the bottom of the trench 2. Outside the upper half section of the trench 2 is an n−-extended drain region 8.
In the n−-extended drain region 8, an n+-drain region 9 is provided. A drain electrode 13, penetrating through an interlayer insulator film 15 and an interlayer insulator film 16 on the film 15, is electrically connected to the n+-drain region 9 on the surface of the substrate 1. A source electrode 14, penetrating through the interlayer insulator film 16, is electrically connected to the top end of the buried electrode 6.
In a MOSFET, lower on-resistance per unit area generally is desirable. A channel width per unit area (hereinafter referred to as a channel density) is an important parameter for determining the on-resistance per unit area and is inversely proportional to the device pitch of the MOSFET. In either of the TLPM's shown in FIGS. 36 and 37, a transistor is formed on the sidewall of the trench 2, which brings the device pitch to on the order of half that of a previous planar power MOSFET. Therefore, in the TLPM, the channel density becomes about twice as great as that of the previous planar power MOSFET, thereby to reduce the on-resistance by half.
A MOSFET, however, is a monopolar device that is operated by majority carriers. A current flows only on the surface of the device. Therefore, reduction in the on-resistance per unit area still has possibilities for improvement. Moreover, when the MOSFETs are mounted in a power IC, the elements are to be isolated from one another by the junction isolation technique. Therefore, integration of the TLPM and a CMOS device for controlling the TLPM has a possibility of causing latchup due to interaction between transistors.
Therefore, an arrangement is proposed in which an insulated gate bipolar transistor (hereinafter referred to as an IGBT) is used instead of the MOSFET to isolate the elements from one another by a dielectric isolation technique. An IGBT, being a bipolar device, has an advantage of allowing on-resistance to be lowered by applying conduction modulation. The applicant has previously filed an application for a patent concerning a planar lateral IGBT to which SOI (Silicon-on-insulator) technology is applied (see Japanese patent publication JP-A-6-151576, for example).
FIG. 38 is a cross-sectional view showing an arrangement of a previous planar lateral IGBT. As shown in FIG. 38, an n-single-crystal silicon semiconductor layer 21 is layered on an oxide film 23 provided on the surface of a supporting substrate 22. In the silicon semiconductor layer 21, an element-forming region 24 is formed like an island while being isolated by a trench isolation region 25. The trench isolation region 25 is formed by an isolation trench 26 penetrating through the silicon semiconductor layer 21 to reach the oxide film 23, a dielectric film 27 provided on the inside face of the isolation trench 26 and polysilicon 28 filling the inside of the dielectric film 27.
In the element-forming region 24, on the surface layer of the silicon semiconductor 21, an n−-drift region 29 is provided. In the n−-drift region 29, a p+-collector region 30 is provided. Moreover, in the element-forming region 24, on the surface layer of the silicon semiconductor 21, a p-base region 31 is provided apart from the n+-drift region 29. In the p-base region 31, an n+-emitter region 32 and a p+-base region 33 are provided.
On the surface of the silicon semiconductor layer 21 between the n+-emitter region 32 and the n−-drift region 29, a gate electrode 35 is provided, with a gate insulator film 34 thereunder. To the p+-collector region 30, a collector electrode 36 is electrically connected. To both of the n+-emitter region 32 and the p+-base region 33, an emitter electrode 37 is electrically connected.
The on-resistance of the planar lateral IGBT shown in FIG. 38, being brought to one fourth that of a planar lateral MOSFET of the same device size, is to be reduced to a half the on-resistance of the TLPM shown in FIG. 36 or FIG. 37. Moreover, an SOI (silicon on insulator) structure, by which the supporting substrate 22 and elements are isolated, can prevent a substrate current. This makes it possible to reduce switching losses and to enhance an operation speed. Furthermore, the introduction of the dielectric isolation technique can eliminate interaction between the IGBT and transistors when IGBTs, or an IGBT and a CMOS, are integrated with each other. This makes it possible to eliminate latchup due to a parasitic thyristor.
In the previous planar lateral IGBT, however, the drift region, being formed laterally, namely, in the direction perpendicular to that of the device thickness, must be extended laterally for enhancing the breakdown voltage. This prevents the IGBT from being highly integrated. Moreover, there also arises a problem that the laterally extended drift region causes an increase in the device pitch, which in turn results in an increase in on-resistance.
Objects and Summary of the Invention
The invention was made in view of the above problems with an object of providing a semiconductor device provided with a trench lateral IGBT (hereinafter referred to as a TL-IGBT) having a small device pitch by which the IGBT can be highly integrated. Moreover, it is also an object of the invention to eliminate the substrate current of the TL-IGBT in a semiconductor device provided with the TL-IGBT, to enable realization of a reduction in switching losses and a high operation speed.
A further object of the invention to reduce on-resistance in the semiconductor device provided with the TL-IGBT to be less than those in a TLPM and a planar lateral IGBT. In addition, it is an object of the invention to prevent latchup in a semiconductor device in which the TL-IGBTs are integrated together, or to prevent malfunctions due to interaction between transistors in a semiconductor device in which the TL-IGBT and elements such as CMOS devices are integrated together.
In order to achieve the above objectives, a semiconductor device according to a first embodiment of the invention includes a collector region of a first conductivity type provided on the underside of a bottom of a trench formed in a semiconductor layer. An emitter region of a second conductivity type is provided on the outside of the trench in a surface layer of the semiconductor layer. A base region of the first conductivity type is provided between the emitter region and the collector region. Adrift region of the second conductivity type is provided between the base region and the collector region. A gate insulator film is provided on the inside of the trench. A gate electrode is provided on the inside of the gate insulator film. An interlayer insulator film is provided on the inside of the gate electrode. A buried electrode is provided on the inside of the interlayer insulator film and electrically connected to the collector region at the bottom of the trench. A collector electrode is electrically connected to the buried electrode. An emitter electrode is electrically connected to both of the emitter region and the base region.
In the this embodiment, the semiconductor device may have an arrangement further including an insulator film thicker than the gate insulator film in a lower half section of the trench. Alternatively, it may have an arrangement that including a buffer region of the second conductivity type surrounding the collector region. The semiconductor device may be formed in an element-forming region isolated from surroundings by a trench isolation region in which a conductive material fills an isolation trench with an insulator film provided at the trench boundary, the isolation trench penetrating through the semiconductor layer. The semiconductor layer may be made of a silicon semiconductor layered on an insulation layer.
The semiconductor device according to the first embodiment is provided with a TL-IGBT having a gate electrode in the trench formed in the semiconductor substrate, and having a current path near the sidewall or the bottom of the trench. Further, in the semiconductor device according to this embodiment, the TL-IGBT is formed on an SOI substrate.
Also to achieve the above objectives, a semiconductor device according to a second embodiment includes an emitter region of a second conductivity type provided on the underside of a bottom of a trench formed in a semiconductor layer. A collector region of a first conductivity type is provided on the outside of the trench in a surface layer of the semiconductor layer. Abase region of the first conductivity type is provided between the emitter region and the collector region. A drift region of the second conductivity type is provided between the base region and the collector region. A gate insulator film is provided on the inside of the trench. A gate electrode is provided on the inside of the gate insulator film. An interlayer insulator film is provided on the inside of the gate electrode. A buried electrode, provided on the inside of the interlayer insulator film, is electrically connected to the emitter region at the bottom of the trench. An emitter electrode is electrically connected to the buried electrode. A collector electrode is electrically connected to the collector region.
In the second embodiment, the semiconductor device may have an arrangement that also includes an insulator film thicker than the gate insulator film in an upper half section of the trench, and/or it may have an arrangement that includes a buffer region of the second conductivity type surrounding the collector region. Moreover, the semiconductor device may be formed in an element-forming region isolated from its surroundings by a trench isolation region in which a conductive material fills an isolation trench with an insulator film provided between the conductive material and the surroundings. The isolation trench penetrates through the semiconductor layer. The semiconductor layer may be made of a silicon semiconductor layered on an insulation layer.
More specifically according to the second embodiment, a semiconductor device is obtained which is provided with the TL-IGBT having the gate electrode in the trench formed in the semiconductor substrate, and having a current path near the sidewall or the bottom of the trench. Further, a semiconductor device is obtained in which the TL-IGBT is formed on an SOI substrate.
Moreover, in order to achieve the above objectives, the semiconductor device according to a third embodiment has a silicon semiconductor layer layered on an insulation layer, with the silicon layer being divided into a plurality of element-forming regions. The element-forming regions are isolated from each other by dielectric isolation with a trench isolation region in which a conductive material fills an isolation trench with an insulator film. The isolation trench penetrates through the semiconductor layer. In a first of the element-forming regions, the semiconductor device according to the first embodiment is formed. In a second of the element-forming regions, the semiconductor device according to the first embodiment with a conductivity type different from that of the semiconductor device formed in the first element-forming region is formed. Alternatively, a semiconductor device according to the first embodiment and a semiconductor device according to the second embodiment may be formed, respectively, in the first element-forming region and the second element-forming region, which are isolated from each other by dielectric isolation. As another alternative, the respective semiconductor devices formed in the first element-forming region and the second element-forming region may be the semiconductor devices according to the second embodiment, with conductivity types being different from each other.
More specifically according to the third embodiment, a semiconductor device is obtained with an arrangement in which the TL-IGBTs are integrated together, with each being isolated from others by a dielectric isolation technique.
Furthermore, in order to achieve the above objectives, according to the semiconductor device of a fourth embodiment, a silicon semiconductor layer layered on an insulation layer is divided into a plurality of element-forming regions isolated from each other by dielectric isolation with a trench isolation region in which a conductive material fills an isolation trench, with an insulator film provided at the trench boundary, the isolation trench penetrating through the semiconductor layer. In a first of a plurality of the element-forming regions, the semiconductor device according to the first or the second embodiment is formed, and in a second of the element-forming regions, one or both of a planar p-channel MOSFET and a planar n-channel MOSFET are formed for controlling the semiconductor device formed in the first element-forming region. In the fourth embodiment, the p-channel MOSFET and the n-channel MOSFET may be formed in their respective different element-forming regions, isolated from each other by dielectric isolation. Also, according to the fourth embodiment, a semiconductor device is obtained with an arrangement in which the TL-IGBT and CMOS devices are integrated together with each being isolated from others by dielectric isolation.